When testing a memory device, it is generally necessary to test several different memory array patterns on a RAM device to ensure correct functionality. Each memory array pattern requires a large number of test vectors. Memory testers typically have specialized logic that is used to generate the memory array test patterns automatically, with very little vector memory requirement. General purpose logic testers (e.g., those used for testing dual-port SRAMs or embedded SRAMs) typically do not have the test capability to provide the number of test patterns required. As a result, a large memory on the tester device may be required to test the memory array. By implementing the vectors on the memory of the tester device, long test times may be required (generally caused by the additional time needed to load more than one vector data block to the tester) or expensive vector memory expansion may be required. A pseudo-random address generator is sometimes used to reduce the memory overhead or test time. However, a pseudo-random address generator does not give full coverage of all required memory array addressing sequences.
Conventional approaches to testing memories may include (i) built-in address counters in the memory device being tested allow cycling through all addresses in a linear sequence, (ii) memory testers used to generate array patterns and (iii) additional memory that may be added to logic testers to enable larger vector sets without the need to reload vectors during testing, however the additional memory adds expense to the tester device.